The most important trend in the semiconductor industry over the last several decades has been a continued striving to improve device performance, which also requires a continuous decrease of semiconductor device feature sizes. In present day semiconductor devices, it is common to encounter feature size in the deep sub-micron range. With this decrease in feature size, sub-micron metal interconnects become increasingly more important. Ideally, a metal layer should be evenly deposited and should fill the profile for the metal line with equal metal density. However, for the sizes of sub-micron metal interconnects, poor step coverage of the deposited metal layer is often encountered. Moreover, when the thickness of the sub-micron metal interconnects is increased to solve the RC delay problem, the poor step coverage problem will only become more serious.